Datasheet > 74LCX139_06

74LCX139_06

更新时间： 2024-11-04 04:47:43

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
17页	315K
描述
Low voltage CMOS Dual 2 to 4 decoder / demultiplexer

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74LCX139_06 数据手册

74LCX139

Low voltage CMOS

Dual 2 to 4 decoder / demultiplexer

Features

■ 5V tolerant inputs

■ High speed:

– t = 6.2ns (Max) at V = 3V

■ Power down protection on inputs and outputs

■ Symmetrical output impedance:

SO-16

TSSOP16

– |I | = I = 24mA (Min) at V = 3V

■ PCI bus levels guaranteed at 24mA

■ Balanced propagation delays:

Description

– t

≅ t

The 74LCX139 is a low voltage CMOS dual 2 to 4

line Decoder / Demultiplexer fabricated with sub-

micron silicon gate and double-layer metal wiring

PLH

PHL

■ Operating voltage range:

– V (Opr) = 2.0V to 3.6V

C MOS technology.

■ Pin and function compatible with

It is ideal for low power and high speed 3.3V

applications; it can be interfaced to 5V signal

environment for inputs.

74 series 139

■ Latch-up performance exceeds

500mA (JESD 17)

The active low enable input can be used for gating

or as a data input for demultiplexing applications.

While the enable input is held high, all four

outputs are high independently of the other

inputs.

■ ESD performance:

– HBM > 2000V

(MIL STD 883 method 3015); MM > 200V

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Order codes

Part number

Package

SO-16

Packaging

74LCX139MTR

Tape and reel

74LCX139TTR

TSSOP16

July 2006

Rev 4

1/17

www.st.com

12 3 4 5 6 7...17

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