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74LCX138_06 PDF预览

74LCX138_06

更新时间: 2024-11-24 04:47:43
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
17页 309K
描述
Low voltage CMOS 3 to 8 line decoder (Inverter) with 5V tolerant inputs

74LCX138_06 数据手册

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74LCX138  
Low voltage CMOS 3 to 8 line decoder (Inverter)  
with 5V tolerant inputs  
Features  
5V tolerant inputs  
High speed:  
– t = 6.7ns (Max) at V = 3V  
PD  
CC  
Power down protection on inputs and outputs  
Symmetrical output impedance:  
SO-16  
TSSOP16  
– |I | = I = 24mA (Min) at V = 3V  
OH  
OL  
CC  
PCI bus levels guaranteed at 24mA  
Balanced propagation delays:  
Description  
– t  
t  
The 74LCX138 is a low voltage CMOS 3 to 8 line  
decoder (inverting) fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power and high  
speed 3.3V applications; it can be interfaced to  
5V signal environment for inputs.  
PLH  
PHL  
Operating voltage range:  
2
– V (Opr) = 2.0V to 3.6V  
CC  
Pin and function compatible with  
74 series 138  
Latch-up performance exceeds  
If the device is enabled, 3 binary select inputs (A,  
B and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either  
G2A or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go to high.  
500mA (JESD 17)  
ESD performance:  
– HBM > 2000V  
(MIL STD 883 method 3015); MM > 200V  
Three enable inputs are provided to ease  
cascade connection and application of address  
decoders for memory systems.  
It has same speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
Order codes  
Part number  
Package  
SO-16  
Packaging  
74LCX138MTR  
Tape and reel  
Tape and reel  
74LCX138TTR  
TSSOP16  
July 2006  
Rev 5  
1/17  
www.st.com  
17  

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