74LCX125TTR-LF

更新时间： 2024-11-04 13:04:59

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意法半导体 - STMICROELECTRONICS		/
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74LCX125TTR-LF 数据手册

74LCX125

Low voltage CMOS quad bus buffer (3-State)

with 5V tolerant inputs and outputs

Features

■ 5V tolerant inputs and outputs

■ High speed:

– t = 5.2ns (Max) at V = 3V

■ Power down protection on inputs and outputs

■ Symmetrical output impedance:

SO-14

TSSOP14

– |I | = I = 24mA (Min) at V = 3V

■ PCI bus levels guaranteed at 24mA

■ Balanced propagation delays:

Description

– t

≅ t

The 74LCX125 is a low voltage CMOS quad bus

buffer fabricated with sub-micron silicon gate and

double-layer metal wiring C MOS technology. It is

ideal for low power and high speed 3.3V

applications; it can be interfaced to 5V signal

environment for both inputs and outputs.

PLH

PHL

■ Operating voltage range:

– V (Opr) = 2.0V to 3.6V

■ Pin and function compatible with

74 series 125

■ Latch-up performance exceeds

The device requires the 3-STATE control input G

to be set high to place the output in to the high

impedance state.

500mA (JESD 17)

■ ESD performance:

– HBM > 2000V

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

(MIL STD 883 method 3015); MM > 200V

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Order codes

Part number

Package

SO-14

Packaging

74LCX125MTR

Tape and reel

74LCX125TTR

TSSOP14

July 2006

Rev 6

1/16

www.st.com

12 3 4 5 6 7...16

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