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74LCX126SJ PDF预览

74LCX126SJ

更新时间: 2024-11-24 04:37:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 754K
描述
Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

74LCX126SJ 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOP
包装说明:5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.44
Is Samacsys:N控制类型:ENABLE HIGH
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:5.5 ns
传播延迟(tpd):6.6 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
Base Number Matches:1

74LCX126SJ 数据手册

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February 2008  
74LCX126  
Low Voltage Quad Buffer with 5V Tolerant  
Inputs and Outputs  
Features  
General Description  
5V tolerant inputs and outputs  
The LCX126 contains four independent non-inverting  
buffers with 3-STATE outputs. Each output is disabled  
when the associated output-enable (OE) input is LOW.  
The inputs tolerate voltages up to 7V allowing the inter-  
face of 5V systems to 3V systems.  
2.3V–3.6V V specifications provided  
CC  
5.5ns t max. (V = 3.3V), 10µA I max.  
PD  
CC  
CC  
Power down high impedance inputs and outputs  
(1)  
Supports live insertion/withdrawal  
The 74LCX126 is fabricated with an advanced CMOS  
technology to achieve high speed operation while main-  
taining CMOS low power dissipation.  
24mA output drive (V = 3.0V)  
CC  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds JEDEC 78 conditions  
ESD performance:  
– Human body model > 2000V  
– Machine model > 100V  
Leadless DQFN package  
Note:  
1. To ensure the high-impedance state during power up  
or down, OE should be tied to V through a pull-up  
CC  
resistor: the minimum value of the resistor is  
determined by the current-sourcing capability of the  
driver.  
Ordering Information  
Package  
Order Number  
74LCX126M  
Number  
Package Description  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX126SJ  
M14D  
(2)  
74LCX126BQX  
MLP14A  
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC  
MO-241, 2.5 x 3.0mm  
74LCX126MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Note:  
2. DQFN package available in Tape and Reel only.  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©2000 Fairchild Semiconductor Corporation  
74LCX126 Rev. 1.5.0  
www.fairchildsemi.com  

74LCX126SJ 替代型号

型号 品牌 替代类型 描述 数据表
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