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74LCX10MX_NL PDF预览

74LCX10MX_NL

更新时间: 2024-11-04 13:02:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
8页 109K
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74LCX10MX_NL 数据手册

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June 2000  
Revised February 2005  
74LCX10  
Low Voltage Triple 3-Input NAND Gate  
with 5V Tolerant Inputs  
General Description  
The LCX10 contains three 3-input NAND gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V sys-  
tems to 3V systems.  
Features  
5V tolerant inputs  
2.3V–3.6V VCC specifications provided  
4.9 ns tPD max (VCC 3.3V), 10 A ICC max  
Power down high impedance inputs and outputs  
The 74LCX10 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
24 mA output drive (VCC 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model 2000V  
Machine model 200V  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX10M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX10SJ  
74LCX10MTC  
MTC14  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Truth Table  
On An Bn Cn  
Pin Names  
An, Bn, Cn  
On  
Description  
Inputs  
An  
Bn  
Cn  
On  
Outputs  
X
X
L
X
L
L
X
X
H
H
H
H
L
X
H
H
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Immaterial  
© 2005 Fairchild Semiconductor Corporation  
DS500453  
www.fairchildsemi.com  

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