74LCX10MX_NL

更新时间： 2024-11-20 13:02:55

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
8页	109K
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中文翻译

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数据手册

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74LCX10MX_NL 数据手册

June 2000

Revised February 2005

74LCX10

Low Voltage Triple 3-Input NAND Gate

with 5V Tolerant Inputs

General Description

The LCX10 contains three 3-input NAND gates. The inputs

tolerate voltages up to 7V allowing the interface of 5V sys-

tems to 3V systems.

Features

■ 5V tolerant inputs

■ 2.3V–3.6V V_CCspecifications provided

■ 4.9 ns t_PDmax (V_CC3.3V), 10 A I_CCmax

■ Power down high impedance inputs and outputs

The 74LCX10 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

■

24 mA output drive (V_CC3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model 2000V

Machine model 200V

Ordering Code:

Order Number Package Number

Package Description

74LCX10M

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX10SJ

74LCX10MTC

MTC14

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

Connection Diagram

IEEE/IEC

Pin Descriptions

Truth Table

O_nA_nB_nC_n

Pin Names

A_n, B_n, C_n

O_n

Description

Inputs

A_n

B_n

C_n

O_n

Outputs

HIGH Voltage Level

LOW Voltage Level

Immaterial

DS500453

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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74LCX112M	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
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74LCX112MTC	FAIRCHILD	获取价格	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112MTC	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16