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74LCX112MTC PDF预览

74LCX112MTC

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 101K
描述
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs

74LCX112MTC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.14
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:150000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:2功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:7.5 ns传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:4.4 mm
最小 fmax:150 MHzBase Number Matches:1

74LCX112MTC 数据手册

 浏览型号74LCX112MTC的Datasheet PDF文件第2页浏览型号74LCX112MTC的Datasheet PDF文件第3页浏览型号74LCX112MTC的Datasheet PDF文件第4页浏览型号74LCX112MTC的Datasheet PDF文件第5页浏览型号74LCX112MTC的Datasheet PDF文件第6页浏览型号74LCX112MTC的Datasheet PDF文件第7页 
June 1998  
Revised February 2001  
74LCX112  
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop  
with 5V Tolerant Inputs  
General Description  
Features  
5V tolerant inputs  
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-  
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,  
Q outputs. These devices are edge sensitive and change  
state on the negative going transition of the clock pulse.  
Clear and preset are independent of the clock and accom-  
plished by a low logic level on the corresponding input.  
LCX devices are designed for low voltage (3.3V or 2.5)  
operation with the added capability of interfacing to a 5V  
signal environment.  
2.3V–3.6V VCC specifications provided  
7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
±24 mA output drive (VCC = 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The 74LCX112 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 2000V  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX112M  
M16A  
M16D  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX112SJ  
74LCX112MTC  
MTC16  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
J1, J2, K1, K2  
CP1, CP2  
Description  
Data Inputs  
Clock Pulse Inputs (Active Falling Edge)  
Direct Clear Inputs (Active LOW)  
Direct Set Inputs (Active LOW)  
Outputs  
C
D1, CD2  
D1, SD2  
Q1, Q2, Q1, Q2  
S
© 2001 Fairchild Semiconductor Corporation  
DS012424  
www.fairchildsemi.com  

74LCX112MTC 替代型号

型号 品牌 替代类型 描述 数据表
74LCX112MTCX FAIRCHILD

完全替代

J-K-Type Flip-Flop
74LCX112MTC ONSEMI

类似代替

低电压双 J-K 负向边触发触发器,带 5V 耐压输入
SN74LVC112APWR TI

功能相似

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

与74LCX112MTC相关器件

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74LCX112MTCX ROCHESTER

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74LCX112MTCX_NL FAIRCHILD

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J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Out
74LCX112MX FAIRCHILD

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74LCX112MX ONSEMI

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低电压双 J-K 负向边触发触发器,带 5V 耐压输入
74LCX112SJ FAIRCHILD

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Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112SJ ROCHESTER

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LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LCX112SJX FAIRCHILD

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J-K-Type Flip-Flop