Datasheet > 74LCX11_08

74LCX11_08

更新时间： 2024-11-04 12:23:31

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
13页	798K
描述
Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74LCX11_08 数据手册

February 2008

74LCX11

Low Voltage Triple 3-Input AND Gate with 5V

Tolerant Inputs

Features

General Description

■ 5V tolerant inputs

The LCX11 is a triple 3-input AND gate with buffered

outputs. LCX devices are designed for low voltage (2.5V

or 3.3V) operation with the added capability of interfac-

ing to a 5V signal environment.

■ 2.3V–3.6V V specifications provided

■ 6.0ns t max. (V = 3.3V), 10µA I max.

■ Power down high impedance inputs and outputs

24mA output drive (V = 3.0V)

The 74LCX11 is fabricated with advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

■

■ Implements proprietary noise/EMI reduction circuitry

■ Latch-up performance exceeds JEDEC 78 conditions

■ ESD performance:

– Human body model > 2000V

– Machine model > 200V

■ Leadless DQFN package

Ordering Information

Package

Order Number

74LCX11M

Number

Package Description

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX11SJ

M14D

(1)

74LCX11BQX

MLP14A

14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX11MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Note:

1. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74LCX11 Rev. 1.6.0

www.fairchildsemi.com

12 3 4 5 6 7...13

中文翻译

下载PDF

与74LCX11_08相关器件

型号	品牌	获取价格	描述	数据表
74LCX112	FAIRCHILD	获取价格	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112M	FAIRCHILD	获取价格	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112M	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LCX112M	ONSEMI	获取价格	低电压双 J-K 负向边触发触发器，带 5V 耐压输入
74LCX112MTC	FAIRCHILD	获取价格	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112MTC	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LCX112MTC	ONSEMI	获取价格	低电压双 J-K 负向边触发触发器，带 5V 耐压输入
74LCX112MTC_NL	FAIRCHILD	获取价格	J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Out
74LCX112MTCX	FAIRCHILD	获取价格	J-K-Type Flip-Flop
74LCX112MTCX	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16