74LCX112

更新时间： 2024-11-19 22:45:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
9页	101K
描述
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs

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中文翻译

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数据手册

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74LCX112 数据手册

June 1998

Revised February 2001

74LCX112

Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop

with 5V Tolerant Inputs

General Description

Features

■ 5V tolerant inputs

The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-

pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,

Q outputs. These devices are edge sensitive and change

state on the negative going transition of the clock pulse.

Clear and preset are independent of the clock and accom-

plished by a low logic level on the corresponding input.

LCX devices are designed for low voltage (3.3V or 2.5)

operation with the added capability of interfacing to a 5V

signal environment.

■ 2.3V–3.6V V_CCspecifications provided

■ 7.5 ns t_PDmax (V_CC= 3.3V), 10 µA I_CCmax

■ Power down high impedance inputs and outputs

■ ±24 mA output drive (V_CC= 3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

The 74LCX112 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Human body model > 2000V

Machine model > 2000V

Ordering Code:

Order Number Package Number

Package Description

74LCX112M

M16A

M16D

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX112SJ

74LCX112MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

J₁, J₂, K₁, K₂

CP₁, CP₂

Description

Data Inputs

Clock Pulse Inputs (Active Falling Edge)

Direct Clear Inputs (Active LOW)

Direct Set Inputs (Active LOW)

Outputs

_D1, C_D2

_D1, S_D2

Q₁, Q₂, Q₁, Q₂

DS012424

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与74LCX112相关器件

型号	品牌	获取价格	描述	数据表
74LCX112M	FAIRCHILD	获取价格	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112M	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LCX112M	ONSEMI	获取价格	低电压双 J-K 负向边触发触发器，带 5V 耐压输入
74LCX112MTC	FAIRCHILD	获取价格	Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112MTC	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LCX112MTC	ONSEMI	获取价格	低电压双 J-K 负向边触发触发器，带 5V 耐压输入
74LCX112MTC_NL	FAIRCHILD	获取价格	J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Out
74LCX112MTCX	FAIRCHILD	获取价格	J-K-Type Flip-Flop
74LCX112MTCX	ROCHESTER	获取价格	LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
74LCX112MTCX	ONSEMI	获取价格	低电压双 J-K 负向边触发触发器，带 5V 耐压输入

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