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74HCT137 PDF预览

74HCT137

更新时间: 2024-11-19 22:56:19
品牌 Logo 应用领域
恩智浦 - NXP 解复用器锁存器
页数 文件大小 规格书
19页 105K
描述
3-to-8 line decoder/demultiplexer with address latches; inverting

74HCT137 数据手册

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74HC137  
3-to-8 line decoder, demultiplexer with address latches;  
inverting  
Rev. 03 — 11 November 2004  
Product data sheet  
1. General description  
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power  
Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address  
inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit  
storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active  
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present  
at the inputs before this transition, is stored in the latches. Further address changes are  
ignored as long as LE remains HIGH.  
The output enable input (E1 and E2) controls the state of the outputs independent of the  
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.  
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state  
systems and strobed (stored address) applications in bus oriented systems.  
2. Features  
Combines 3-to-8 decoder with 3-bit latch  
Multiple input enable for easy expansion or independent controls  
Active LOW mutually exclusive outputs  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  

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