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74HCT138N,652 PDF预览

74HCT138N,652

更新时间: 2024-11-20 18:58:11
品牌 Logo 应用领域
恩智浦 - NXP 驱动输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
19页 224K
描述
74HCT138N

74HCT138N,652 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.59
其他特性:3 ENABLE INPUTS系列:HCT
输入调节:STANDARDJESD-30 代码:R-PDIP-T16
JESD-609代码:e4长度:19.025 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:53 ns传播延迟(tpd):53 ns
认证状态:Not Qualified座面最大高度:4.2 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.62 mmBase Number Matches:1

74HCT138N,652 数据手册

 浏览型号74HCT138N,652的Datasheet PDF文件第2页浏览型号74HCT138N,652的Datasheet PDF文件第3页浏览型号74HCT138N,652的Datasheet PDF文件第4页浏览型号74HCT138N,652的Datasheet PDF文件第5页浏览型号74HCT138N,652的Datasheet PDF文件第6页浏览型号74HCT138N,652的Datasheet PDF文件第7页 
74HC138; 74HCT138  
3-to-8 line decoder/demultiplexer; inverting  
Rev. 5 — 26 January 2015  
Product data sheet  
1. General description  
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2)  
to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs  
(E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.  
This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines)  
decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output  
demultiplexer by using one of the active LOW enable inputs as the data input and the  
remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of  
current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Complies with JEDEC standard no. 7A  
Input levels:  
For 74HC138: CMOS level  
For 74HCT138: TTL level  
Demultiplexing capability  
Multiple input enable for easy expansion  
Ideal for memory chip select decoding  
Active LOW mutually exclusive outputs  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC138N  
40 C to +125 C  
40 C to +125 C  
40 C to +125 C  
DIP16  
plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
74HCT138N  
74HC138D  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
SOT338-1  
74 HCT138D  
74HC138DB  
74HCT138DB  
SSOP16  
plastic shrink small outline package; 16 leads;  
body width 5.3 mm  
 
 
 

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