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74HC4020PW-Q100 PDF预览

74HC4020PW-Q100

更新时间: 2024-11-19 01:07:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
18页 781K
描述
14-stage binary ripple counter

74HC4020PW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.59
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:ASYNCHRONOUS
湿度敏感等级:1位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):210 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:4.4 mm最小 fmax:24 MHz
Base Number Matches:1

74HC4020PW-Q100 数据手册

 浏览型号74HC4020PW-Q100的Datasheet PDF文件第2页浏览型号74HC4020PW-Q100的Datasheet PDF文件第3页浏览型号74HC4020PW-Q100的Datasheet PDF文件第4页浏览型号74HC4020PW-Q100的Datasheet PDF文件第5页浏览型号74HC4020PW-Q100的Datasheet PDF文件第6页浏览型号74HC4020PW-Q100的Datasheet PDF文件第7页 
74HC4020-Q100;  
74HCT4020-Q100  
14-stage binary ripple counter  
Rev. 1 — 23 May 2013  
Product data sheet  
1. General description  
The 74HC4020-Q100; 74HCT4020-Q100 are 14-stage binary ripple counters with a clock  
input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel  
outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of  
CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of  
the state of CP. Each counter stage is a static toggle flip-flop.. Inputs include clamp  
diodes. This enables the use of current limiting resistors to interface inputs to voltages in  
excess of VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Input levels:  
For 74HC4020-Q100: CMOS level  
For 74HCT4020-Q100: TTL level  
Complies with JEDEC standard no. 7A  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
3. Applications  
Frequency dividing circuits  
Time delay circuits  
Control counters  

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