5秒后页面跳转
74HC4024N PDF预览

74HC4024N

更新时间: 2024-11-19 22:53:15
品牌 Logo 应用领域
恩智浦 - NXP 计数器逻辑集成电路光电二极管
页数 文件大小 规格书
18页 97K
描述
7-stage binary ripple counter

74HC4024N 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 不含铅
是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:MO-001包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.34计数方向:UP
系列:HC/UHJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.025 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
位数:7功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):265 ns认证状态:Not Qualified
座面最大高度:4.2 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:24 MHz
Base Number Matches:1

74HC4024N 数据手册

 浏览型号74HC4024N的Datasheet PDF文件第2页浏览型号74HC4024N的Datasheet PDF文件第3页浏览型号74HC4024N的Datasheet PDF文件第4页浏览型号74HC4024N的Datasheet PDF文件第5页浏览型号74HC4024N的Datasheet PDF文件第6页浏览型号74HC4024N的Datasheet PDF文件第7页 
74HC4024  
7-stage binary ripple counter  
Rev. 03 — 12 November 2004  
Product data sheet  
1. General description  
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024  
of the 4000B series. The 74HC4024 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding  
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to  
Q6).  
The counter advances on the HIGH-to-LOW transition of CP.  
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the  
state of CP.  
Each counter stage is a static toggle flip-flop.  
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock  
rise and fall times.  
2. Features  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  
3. Applications  
Frequency dividing circuits  
Time delay circuits.  

74HC4024N 替代型号

型号 品牌 替代类型 描述 数据表
74HC4024D NXP

类似代替

7-stage binary ripple counter
CD74HC4024E TI

功能相似

High Speed CMOS Logic 7-Stage Binary Ripple Counter
M74HC4024B1R STMICROELECTRONICS

功能相似

7 STAGE BINARY COUNTER

与74HC4024N相关器件

型号 品牌 获取价格 描述 数据表
74HC4024NB NXP

获取价格

IC HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDIP14, Counter
74HC4024PW NXP

获取价格

7-stage binary ripple counter
74HC4024PW,112 NXP

获取价格

74HC4024 - 7-stage binary ripple counter TSSOP 14-Pin
74HC4024PW,118 NXP

获取价格

74HC4024 - 7-stage binary ripple counter TSSOP 14-Pin
74HC4024PW-Q100 NXP

获取价格

IC BINARY COUNTER, Counter
74HC4024PW-Q100J NXP

获取价格

74HC4024-Q100 - 7-stage binary ripple counter TSSOP 14-Pin
74HC4024-Q100 NEXPERIA

获取价格

7-stage binary ripple counter
74HC4040 NXP

获取价格

12-stage binary ripple counter
74HC4040BQ NXP

获取价格

12-stage binary ripple counter
74HC4040BQ NEXPERIA

获取价格

12-stage binary ripple counterProduction