74HC4040

更新时间： 2024-09-23 22:53:15

品牌	Logo	应用领域
恩智浦 - NXP		计数器
页数	文件大小	规格书
24页	134K
描述
12-stage binary ripple counter

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数据手册

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74HC4040 数据手册

74HC4040; 74HCT4040

12-stage binary ripple counter

Rev. 03 — 14 September 2005

Product data sheet

1. General description

The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin

compatible with the HEF4040B series. They are speciﬁed in compliance with JEDEC

standard no. 7A.

The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),

an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to

Q11). The counter advances on the HIGH-to-LOW transition of CP.

A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the

state of CP.

Each counter stage is a static toggle ﬂip-ﬂop.

2. Features

■ Multiple package options

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM JESD22-A114-C exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Applications

■ Frequency dividing circuits

■ Time delay circuits

■ Control counters

4. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns.

Symbol Parameter

Type 74HC4040

t_PHL, t_PLHpropagation delay

Conditions

Min Typ Max Unit

CP to Q0

C_L= 15 pF; V_CC= 5 V

Qn to Qn+1

12 3 4 5 6 7...24

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