Datasheet > 74HC4024D-Q100

74HC4024D-Q100

更新时间： 2024-11-18 01:16:03

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	219K
描述
7-stage binary ripple counter

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74HC4024D-Q100 数据手册

74HC4024-Q100

7-stage binary ripple counter

Rev. 2 — 23 November 2018

Product data sheet

1. General description

The 74HC4024-Q100 is a 7-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The

counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages

and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle

flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to

interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Low-power dissipation

Complies with JEDEC standard no. 7A

CMOS input levels

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

3. Applications

•

Frequency dividing circuits

Time delay circuits.

4. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

-40 °C to +125 °C

Name

Description

Version

74HC4024D-Q100

SO14

plastic small outline package;

14 leads; body width 3.9 mm

SOT108-1

12 3 4 5 6 7...13

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