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74HC173D PDF预览

74HC173D

更新时间： 2024-11-01 12:52:47
品牌 Logo 应用领域
恩智浦 - NXP 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
3页 46K
描述
Quad D-type flip-flop; positive-edge trigger; 3-state

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中文翻译

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74HC173D 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.06Is Samacsys：N
其他特性：WITH HOLD MODE系列：HC/UH
JESD-30 代码：R-PDSO-G16长度：9.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：24000000 Hz最大I（ol）：0.006 A
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：2/6 V传播延迟（tpd）：53 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：NICKEL/PALLADIUM/GOLD (NI/PD/AU)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：60 MHzBase Number Matches：1

74HC173D 数据手册

 浏览型号74HC173D的Datasheet PDF文件第2页浏览型号74HC173D的Datasheet PDF文件第3页 
Philips Semiconductors  
Product specification  
Quad D-type flip-flop; positive-edge trigger; 3-state  
74HC/HCT173  
synchronously with the LOW-to-HIGH clock (CP)  
FEATURES  
transition. When one or both En inputs are HIGH one  
set-up time prior to the LOW-to-HIGH clock transition, the  
register will retain the previous data. Data inputs and clock  
enable inputs are fully edge-triggered and must be stable  
only one set-up time prior to the LOW-to-HIGH clock  
transition.  
• Gated input enable for hold (do nothing) mode  
• Gated output enable control  
• Edge-triggered D-type register  
• Asynchronous master reset  
• Output capability: bus driver  
• ICC category: MSI  
The master reset input (MR) is an active HIGH  
asynchronous input. When MR is HIGH, all four flip-flops  
are reset (cleared) independently of any other input  
condition.  
GENERAL DESCRIPTION  
The 3-state output buffers are controlled by a 2-input NOR  
gate. When both output enable inputs (OE1 and OE2) are  
LOW, the data in the register is presented to the Qn  
outputs. When one or both OEn inputs are HIGH, the  
outputs are forced to a high impedance OFF-state. The  
3-state output buffers are completely independent of the  
register operation; the OEn transition does not affect the  
clock and reset operations.  
The 74HC/HCT173 are high-speed Si-gate CMOS devices  
and are pin compatible with low power Schottky TTL  
(LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC/HCT173 are 4-bit parallel load registers with  
clock enable control, 3-state buffered outputs (Q0 to Q3)  
and master reset (MR).  
When the two data enable inputs (E1 and E2) are LOW, the  
data on the Dn inputs is loaded into the register  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PHL/ tPLH  
PARAMETER  
propagation delay  
CONDITIONS  
UNIT  
HC  
HCT  
t
CL = 15 pF; VCC = 5 V  
CP to Qn  
MR to Qn  
17  
13  
17  
17  
ns  
ns  
fmax  
CI  
maximum clock frequency  
input capacitance  
88  
3.5  
20  
88  
MHz  
pF  
3.5  
20  
CPD  
power dissipation  
notes 1 and 2  
pF  
capacitance per flip-flop  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
2
∑ (CL × VCC × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC −1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
2
123

中文翻译

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74HC173D 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC173M96G4 TI

类似代替

 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State
CD74HC173M96 TI

功能相似

 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

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