Datasheet > 74AUP2G17GN,132

74AUP2G17GN,132

更新时间： 2024-11-11 14:47:03

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
21页	211K
描述
74AUP2G17 - Low-power dual Schmitt trigger SON 6-Pin

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

74AUP2G17GN,132 技术参数

74AUP2G17

Low-power dual Schmitt trigger

Rev. 6 — 4 December 2012

Product data sheet

1. General description

The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly

changing input signals into sharply defined, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

The inputs switch at different points for positive and negative-going signals. The difference

between the positive voltage V_T+and the negative voltage V_Tis defined as the input

hysteresis voltage V_H.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial Power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...21

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
74AUP2G17GS	NEXPERIA	获取价格	Low-power dual Schmitt triggerProduction
74AUP2G17GW	NXP	获取价格	Low-power dual Schmitt trigger
74AUP2G17GW	NEXPERIA	获取价格	Low-power dual Schmitt triggerProduction
74AUP2G17GW,125	NXP	获取价格	74AUP2G17 - Low-power dual Schmitt trigger TSSOP 6-Pin
74AUP2G17GW-G	NXP	获取价格	暂无描述
74AUP2G240	NXP	获取价格	Low-power dual inverting buffer/line driver; 3-state
74AUP2G240DC	NXP	获取价格	Low-power dual inverting buffer/line driver; 3-state
74AUP2G240DC	NEXPERIA	获取价格	Low-power dual inverting buffer/line driver; 3-stateProduction
74AUP2G240DC-G	NXP	获取价格	IC AUP/ULP/V SERIES, DUAL 1-BIT DRIVER, INVERTED OUTPUT, PDSO8, 2.30 MM, PLASTIC, MO-187,
74AUP2G240GD	NXP	获取价格	Low-power dual inverting buffer/line driver; 3-state