74AUP2G241

更新时间： 2024-11-11 06:31:51

品牌	Logo	应用领域
恩智浦 - NXP		驱动器
页数	文件大小	规格书
22页	120K
描述
Low-power dual buffer/line driver; 3-state

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74AUP2G241 数据手册

74AUP2G241

Low-power dual buffer/line driver; 3-state

Rev. 03 — 12 January 2009

Product data sheet

1. General description

The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs.

The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH

level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level

at pin 2OE causes output 2Y to assume a high-impedance OFF-state.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

This device has an input-disable feature, which allows ﬂoating input signals. The input 1A

is disabled when the output enable input 1OE is HIGH. The input 2A is disabled when the

output enable input 2OE is LOW.

2. Features

I Wide supply voltage range from 0.8 V to 3.6 V

I High noise immunity

I Complies with JEDEC standards:

N JESD8-12 (0.8 V to 1.3 V)

N JESD8-11 (0.9 V to 1.65 V)

N JESD8-7 (1.2 V to 1.95 V)

N JESD8-5 (1.8 V to 2.7 V)

N JESD8-B (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E Class 3A exceeds 5000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Low static power consumption; I_CC= 0.9 µA (maximum)

I Latch-up performance exceeds 100 mA per JESD 78 Class II

I Inputs accept voltages up to 3.6 V

I Low noise overshoot and undershoot < 10 % of V_CC

I Input-disable feature allows ﬂoating input conditions

I I_OFFcircuitry provides partial Power-down mode operation

12 3 4 5 6 7...22

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