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74ALVCH16841DGG PDF预览

74ALVCH16841DGG

更新时间: 2024-11-19 11:14:23
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 210K
描述
20-bit bus interface D-type latch; 3-stateProduction

74ALVCH16841DGG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.3
其他特性:CAN ALSO OPERATE AT VOLTAGE 3-3.6系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:14 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:2位数:10
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):5.6 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmBase Number Matches:1

74ALVCH16841DGG 数据手册

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74ALVCH16841  
20-bit bus interface D-type latch; 3-state  
Rev. 3 — 12 September 2018  
Product data sheet  
1. General description  
The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch  
and 3-state outputs for bus oriented applications. The two sections of each register are controlled  
independently by the latch enable (nLE) and output enable (nOE) control gates.  
When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the  
outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of  
the flip-flops.  
The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating  
data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down  
resistors.  
2. Features and benefits  
Wide supply voltage range of 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Current drive ±24 mA at VCC = 3.0 V  
MULTIBYTE flow-through standard pin-out architecture  
Low inductance multiple VCC and GND pins for minimize noise and ground bounce  
All data inputs have bushold  
Output drive capability 50 Ω transmission lines at 85 °C  
3-state non-inverting outputs for bus oriented applications  
Complies with JEDEC standards:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V  
CDM JESD22-C101E exceeds 1000 V  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ALVCH16841DGG −40 °C to +85 °C  
TSSOP56  
plastic thin shrink small outline package; 56 leads; SOT364-1  
body width 6.1 mm  
 
 
 

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