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74ALVCH16835ZQLR

更新时间： 2024-11-18 05:05:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器输出元件
页数 文件大小 规格书
17页 487K
描述
18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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74ALVCH16835ZQLR 数据手册

 浏览型号74ALVCH16835ZQLR的Datasheet PDF文件第2页浏览型号74ALVCH16835ZQLR的Datasheet PDF文件第3页浏览型号74ALVCH16835ZQLR的Datasheet PDF文件第4页浏览型号74ALVCH16835ZQLR的Datasheet PDF文件第5页浏览型号74ALVCH16835ZQLR的Datasheet PDF文件第6页浏览型号74ALVCH16835ZQLR的Datasheet PDF文件第7页 
SN74ALVCH16835  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES053J–SEPTEMBER 1995–REVISED OCTOBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
GND  
NC  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 3.6 ns at 3.3 V  
2
3
Y1  
GND  
Y2  
A1  
GND  
A2  
±24-mA Output Drive at 3.3 V  
4
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
5
6
Y3  
A3  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
Y4  
Y5  
Y6  
GND  
Y7  
Y8  
A4  
A5  
A6  
GND  
A7  
9
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DESCRIPTION/ORDERING INFORMATION  
A8  
Y9  
A9  
This 18-bit universal bus driver is designed for 1.65-V  
to 3.6-V VCC operation.  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
Data flow from  
A to Y is controlled by the  
output-enable (OE) input. The device operates in the  
transparent mode when the latch-enable (LE) input is  
high. The A data is latched if the clock (CLK) input is  
held at a high or low logic level. If LE is low, the A  
data is stored in the latch/flip-flop on the low-to-high  
transition of CLK. When OE is high, the outputs are in  
the high-impedance state.  
V
CC  
V
CC  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
To ensure the high-impedance state during power up  
or power down, OE should be tied to VCC through a  
pullup resistor; the minimum value of the resistor is  
determined by the current-sinking capability of the  
driver.  
LE  
Active bus-hold circuitry holds unused or undriven  
inputs at a valid logic state. Use of pullup or pulldown  
resistors with the bus-hold circuitry is not  
recommended.  
NC − No internal connection  
xxxx  
xxxx  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
Tube  
SN74ALVCH16835DL  
SN74ALVCH16835DLR  
SN74ALVCH16835DGGR  
SN74ALVCH16835DGVR  
SN74ALVCH16835KR  
74ALVCH16835ZQLR  
SSOP - DL  
ALVCH16835  
Tape and reel  
Tape and reel  
Tape and reel  
TSSOP - DGG  
ALVCH16835  
VH835  
-40°C to 85°C  
TVSOP - DGV  
VFBGA - GQL  
Tape and reel  
VH835  
VFBGA - ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...17

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