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74ALVC74BQ PDF预览

74ALVC74BQ

更新时间: 2024-11-22 11:12:39
品牌 Logo 应用领域
安世 - NEXPERIA 逻辑集成电路触发器
页数 文件大小 规格书
15页 259K
描述
Dual D-type flip-flop with set and reset; positive-edge triggerProduction

74ALVC74BQ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.37
Is Samacsys:N系列:ALVC/VCX/A
JESD-30 代码:R-PQCC-N14JESD-609代码:e4
长度:3 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):6.2 ns认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
最小 fmax:300 MHzBase Number Matches:1

74ALVC74BQ 数据手册

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74ALVC74  
Dual D-type flip-flop with set and reset; positive-edge trigger  
Rev. 7 — 7 July 2023  
Product data sheet  
1. General description  
The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP),  
set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that  
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in  
the flip-flop and appear at the Q output.  
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 3.6 V  
CMOS low power dissipation  
Overvoltage tolerant inputs to 3.6 V  
Direct interface with TTL levels  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 250 mA per JESD78 Class II.A  
Complies with JEDEC standard:  
JESD8-7 (1.65 to 1.95 V)  
JESD8-5 (2.3 to 2.7 V)  
JESD8C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +125 °C  
Name  
Description  
Version  
74ALVC74D  
74ALVC74PW  
74ALVC74BQ  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
-40 °C to +125 °C  
-40 °C to +125 °C  
TSSOP14  
plastic thin shrink small outline package; 14 leads; SOT402-1  
body width 4.4 mm  
DHVQFN14 plastic dual in-line compatible thermal  
enhanced very thin quad flat package; no leads;  
14 terminals; body 2.5 × 3 × 0.85 mm  
SOT762-1  
 
 
 

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