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74ALVC374D,118 PDF预览

74ALVC374D,118

更新时间: 2024-11-06 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 94K
描述
74ALVC374 - Octal D-type flip-flop; positive-edge trigger; 3-state SOP 20-Pin

74ALVC374D,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:PLASTIC, SO-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.35
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):6.4 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

74ALVC374D,118 数据手册

 浏览型号74ALVC374D,118的Datasheet PDF文件第2页浏览型号74ALVC374D,118的Datasheet PDF文件第3页浏览型号74ALVC374D,118的Datasheet PDF文件第4页浏览型号74ALVC374D,118的Datasheet PDF文件第5页浏览型号74ALVC374D,118的Datasheet PDF文件第6页浏览型号74ALVC374D,118的Datasheet PDF文件第7页 
74ALVC374  
Octal D-type flip-flop; positive-edge trigger; 3-state  
Rev. 02 — 17 October 2007  
Product data sheet  
1. General description  
The 74ALVC374 is an octal D-type flip-flop featuring separate D-type inputs for each  
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an  
outputs enable input (OE) are common to all flip-flops.  
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and  
hold times requirements on the LOW to HIGH CP transition.  
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When  
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE  
input does not affect the state of the flip-flops.  
The 74ALVC374 is functionally identical to the 74ALVC574, but has a different pin  
arrangement.  
2. Features  
Wide supply voltage range from 1.65 V to 3.6 V  
3.6 V tolerant inputs/outputs  
CMOS low power consumption  
Direct interface with TTL levels (2.7 V to 3.6 V)  
Power-down mode  
Latch-up performance exceeds 250 mA  
Complies with JEDEC standards:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A 115-A exceeds 200 V  
 
 

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