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74ALVC16721 PDF预览

74ALVC16721

更新时间: 2024-11-05 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
6页 85K
描述
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs

74ALVC16721 数据手册

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October 2001  
Revised October 2001  
74ALVC16721  
Low Voltage 20-Bit D-Type Flip-Flops  
with 3.6V Tolerant Inputs and Outputs  
General Description  
The ALVC16721 contains twenty non-inverting D-type  
flip-flops with 3-STATE outputs and is intended for bus ori-  
ented applications.  
Features  
1.8V–3.6V VCC supply operation  
3.6V tolerant inputs and outputs  
tPD (CLK to On)  
The 74ALVC16721 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
4.0 ns max for 3.0V to 3.6V VCC  
4.9 ns max for 2.3V to 2.7V VCC  
8.8 ns max for 1.65V to 1.95V VCC  
The 74ALVC16721 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
Uses patented noise/EMI reduction circuitry  
Latchup conforms to JEDEC JED78  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74ALVC16721MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OE  
Output Enable Input (Active LOW)  
CLK  
Clock Input  
D0D19  
O0O19  
CE  
Inputs  
Outputs  
Clock Enable Input (Active LOW)  
© 2001 Fairchild Semiconductor Corporation  
DS500691  
www.fairchildsemi.com  

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