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74ALVC16835MTDX PDF预览

74ALVC16835MTDX

更新时间： 2024-11-09 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器
页数 文件大小 规格书
7页 91K
描述
Bus Driver, CMOS, PDSO56,

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中文翻译

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74ALVC16835MTDX 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.29
Is Samacsys：NJESD-30 代码：R-PDSO-G56
JESD-609代码：e0逻辑集成电路类型：BUS DRIVER
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 V认证状态：Not Qualified
子类别：Bus Driver/Transceivers标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUALBase Number Matches：1

74ALVC16835MTDX 数据手册

 浏览型号74ALVC16835MTDX的Datasheet PDF文件第2页浏览型号74ALVC16835MTDX的Datasheet PDF文件第3页浏览型号74ALVC16835MTDX的Datasheet PDF文件第4页浏览型号74ALVC16835MTDX的Datasheet PDF文件第5页浏览型号74ALVC16835MTDX的Datasheet PDF文件第6页浏览型号74ALVC16835MTDX的Datasheet PDF文件第7页 
September 2001  
Revised February 2002  
74ALVC16835  
Low Voltage 18-Bit Universal Bus Driver  
with 3.6V Tolerant Inputs and Outputs  
General Description  
The ALVC16835 low voltage 18-bit universal bus driver  
combines D-type latches and D-type flip-flops to allow data  
flow in transparent, latched and clocked modes.  
Features  
■ Compatible with PC100 DIMM module specifications  
■ 1.65V to 3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ tPD (CLK to On)  
Data flow is controlled by output-enable (OE), latch-enable  
(LE), and clock (CLK) inputs. The device operates in  
Transparent Mode when LE is held HIGH. The device  
operates in clocked mode when LE is LOW and CLK is tog-  
gled. Data transfers from the Inputs (In) to Ouputs (On) on a  
4.5 ns max for 3.0V to 3.6V VCC  
5.5 ns max for 2.3V to 2.7V VCC  
9.2 ns max for 1.65V to 1.95V VCC  
Positive Edge Transition of the Clock. When OE is LOW,  
the output data is enabled. When OE is HIGH the output  
port is in a high impedance state.  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion/withdrawal (Note 1)  
■ Latchup conforms to JEDEC JED78  
■ ESD performance:  
The 74ALVC16835 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
Human body model > 2000V  
The 74ALVC16835 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Machine model >200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC (OE to GND) through a pulldown resistor;  
the minimum value of the resistor is determined by the current sourcing  
capability of the driver.  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74ALVC16835MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2002 Fairchild Semiconductor Corporation  
DS500645  
www.fairchildsemi.com  
1234567

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74ALVC16838MTD ETC

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 		BUFFER/FLIP-FLOP|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC
74ALVC16839 FAIRCHILD

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 		Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
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74ALVC16839MTDX FAIRCHILD

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