5秒后页面跳转
74AHCT259PW-Q100J PDF预览

74AHCT259PW-Q100J

更新时间: 2024-11-24 19:51:39
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
19页 150K
描述
74AHC(T)259-Q100 - 8-bit addressable latch TSSOP 16-Pin

74AHCT259PW-Q100J 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
针数:16Reach Compliance Code:compliant
风险等级:5.75Base Number Matches:1

74AHCT259PW-Q100J 数据手册

 浏览型号74AHCT259PW-Q100J的Datasheet PDF文件第2页浏览型号74AHCT259PW-Q100J的Datasheet PDF文件第3页浏览型号74AHCT259PW-Q100J的Datasheet PDF文件第4页浏览型号74AHCT259PW-Q100J的Datasheet PDF文件第5页浏览型号74AHCT259PW-Q100J的Datasheet PDF文件第6页浏览型号74AHCT259PW-Q100J的Datasheet PDF文件第7页 
74AHC259-Q100;  
74AHCT259-Q100  
8-bit addressable latch  
Rev. 1 — 22 July 2013  
Product data sheet  
1. General description  
The 74AHC259-Q100; 74AHCT259-Q100 is a high-speed Si-gate CMOS device and is  
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with  
JEDEC standard No. 7-A.  
The 74AHC259-Q100; 74AHCT259-Q100 is a high-speed 8-bit addressable latch  
designed for general purpose storage applications in digital systems. It is a multifunctional  
device capable of storing single-line data in eight addressable latches. It provides a 3-to-8  
decoder and multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates  
an active LOW common reset (MR) for resetting all latches as well as an active LOW  
enable input (LE).  
The 74AHC259-Q100; 74AHCT259-Q100 has four modes of operation:  
In the addressable latch mode, data on the data line (D) is written into the addressed  
latch. The addressed latch follows the data input with all non-addressed latches  
remaining in their previous states.  
In the memory mode, all latches remain in their previous states and are unaffected by  
the data or address inputs.  
In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state  
of the data input (D) with all other outputs in the LOW state.  
In the reset mode, all outputs are LOW and unaffected by the address inputs  
(A0 to A2) and data input (D).  
When operating the 74AHC259-Q100; 74AHCT259-Q100 as an address latch, changing  
more than 1 bit of the address could impose a transient-wrong address. Therefore, only  
change more than 1 bit while in the memory mode.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Balanced propagation delays  
All inputs have Schmitt-trigger actions  
Combines demultiplexer and 8-bit latch  
Serial-to-parallel capability  
 
 

与74AHCT259PW-Q100J相关器件

型号 品牌 获取价格 描述 数据表
74AHCT273 NXP

获取价格

Octal D-type flip-flop with reset; positive-edge trigger
74AHCT273BQ NXP

获取价格

Octal D-type flip-flop with reset; positive-edge trigger
74AHCT273BQ NEXPERIA

获取价格

Octal D-type flip-flop with reset; positive-edge triggerProduction
74AHCT273BQ,115 NXP

获取价格

74AHC(T)273 - Octal D-type flip-flop with reset; positive-edge trigger QFN 20-Pin
74AHCT273BQ-G NXP

获取价格

Octal D-type flip-flop with reset; positive-edge trigger - Description: D-Type Flip-Flop w
74AHCT273BQ-Q100 NXP

获取价格

AHCT/VHCT/VT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC20, 2.50 X 4.50
74AHCT273BQ-Q100 NEXPERIA

获取价格

Octal D-type flip-flop with reset; positive-edge trigger
74AHCT273BQ-Q100X NXP

获取价格

74AHC(T)273-Q100 - Octal D-type flip-flop with reset; positive-edge trigger QFN 20-Pin
74AHCT273D NXP

获取价格

Octal D-type flip-flop with reset; positive-edge trigger
74AHCT273D NEXPERIA

获取价格

Octal D-type flip-flop with reset; positive-edge triggerProduction