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74AHC123ABQ,115 PDF预览

74AHC123ABQ,115

更新时间： 2024-11-04 15:26:35
品牌 Logo 应用领域
恩智浦 - NXP 时钟PC逻辑集成电路
页数 文件大小 规格书
22页 315K
描述
74AHC(T)123A - Dual retriggerable monostable multivibrator with reset QFN 16-Pin

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74AHC123ABQ,115 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFN包装说明：HVQCCN, LCC16,.1X.14,20
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：7.61
系列：AHC/VHC/H/U/VJESD-30 代码：R-PQCC-N16
JESD-609代码：e4长度：3.5 mm
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR湿度敏感等级：1
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC16,.1X.14,20封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：2/5.5 V传播延迟（tpd）：30 ns
认证状态：Not Qualified座面最大高度：1 mm
子类别：Prescaler/Multivibrators最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：2.5 mmBase Number Matches：1

74AHC123ABQ,115 数据手册

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74AHC123A; 74AHCT123A  
Dual retriggerable monostable multivibrator with reset  
Rev. 4 — 8 November 2011  
Product data sheet  
1. General description  
The 74AHC123A; 74AHCT123A are high-speed Si-gate CMOS devices and are pin  
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard no. 7A.  
The 74AHC123A; 74AHCT123A are dual retriggerable monostable multivibrators with  
output pulse width control by three methods. The basic pulse time is programmed by  
selection of an external resistor (REXT) and capacitor (CEXT). The external resistor and  
capacitor are normally connected as shown in Figure 11.  
Once triggered, the basic output pulse width may be extended by retriggering the gated  
active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating  
this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as  
desired. Alternatively an output delay can be terminated at any time by a LOW-going edge  
on input nRD, which also inhibits the triggering.  
An internal connection from nRD to the input gate makes it possible to trigger the circuit by  
a positive-going signal at input nRD as shown in Table 3. Figure 8 and Figure 9 illustrate  
pulse control by retriggering and early reset. The basic output pulse width is essentially  
determined by the value of the external timing components REXT and CEXT. When  
CEXT 10 nF, the typical output pulse width is defined as: tW = REXT CEXT where  
tW = pulse width in ns; REXT = external resistor in k; CEXT = external capacitor in pF.  
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and  
fall times.  
2. Features and benefits  
All inputs have a Schmitt-trigger action  
Inputs accept voltages higher than VCC  
DC triggered from active HIGH or active LOW inputs  
Retriggerable for very long pulses up to 100 % duty factor  
Direct reset terminates output pulse  
For 74AHC123A only: operates with CMOS input levels  
For 74AHCT123A only: operates with TTL input levels  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
 
 
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