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74AHC123APW-Q100 PDF预览

74AHC123APW-Q100

更新时间： 2024-11-04 12:32:31
品牌 Logo 应用领域
恩智浦 - NXP 振荡器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
22页 326K
描述
Dual retriggerable monostable multivibrator with reset

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74AHC123APW-Q100 技术参数

生命周期：Transferred包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.57系列：AHC/VHC/H/U/V
JESD-30 代码：R-PDSO-G16长度：5 mm
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR数据/时钟输入次数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：30 ns
筛选级别：AEC-Q100座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

74AHC123APW-Q100 数据手册

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74AHC123A-Q100;  
74AHCT123A-Q100  
Dual retriggerable monostable multivibrator with reset  
Rev. 1 — 23 May 2013  
Product data sheet  
1. General description  
The 74AHC123A-Q100; 74AHCT123A-Q100 are high-speed Si-gate CMOS devices and  
are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in  
compliance with JEDEC standard no. 7A.  
The 74AHC123A-Q100; 74AHCT123A-Q100 are dual retriggerable monostable  
multivibrators with output pulse width control by three methods. The selection of an  
external resistor (Rext) and capacitor (Cext) program the basic pulse time. The external  
resistor and capacitor are normally connected as shown in Figure 11.  
Once triggered, the basic output pulse width may be extended by retriggering the gated  
active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating  
this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as  
desired. Alternatively an output delay can be terminated at any time by a LOW-going edge  
on input nRD, which also inhibits the triggering.  
An internal connection from nRD to the input gate makes it possible to trigger the circuit by  
a positive-going signal at input nRD as shown in Table 3. Figure 8 and Figure 9 illustrate  
pulse control by retriggering and early reset. The values of the external timing  
components Rext and Cext, determine the basic output pulse width. When Cext 10 nF, the  
typical output pulse width is defined as: tW = Rext Cext where tW = pulse width in ns;  
R
ext = external resistor in k; Cext = external capacitor in pF. Schmitt-trigger action at all  
inputs makes the circuit highly tolerant to slower input rise and fall times.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
All inputs have a Schmitt-trigger action  
Inputs accept voltages higher than VCC  
DC triggered from active HIGH or active LOW inputs  
Retriggerable for very long pulses up to 100 % duty factor  
Direct reset terminates output pulse  
For 74AHC123A-Q100 only: operates with CMOS input levels  
For 74AHCT123A-Q100 only: operates with TTL input levels  
ESD protection:  
1234567...22

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