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72281L10PFGI8 PDF预览

72281L10PFGI8

更新时间: 2024-09-16 08:40:07
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
26页 197K
描述
FIFO

72281L10PFGI8 数据手册

 浏览型号72281L10PFGI8的Datasheet PDF文件第2页浏览型号72281L10PFGI8的Datasheet PDF文件第3页浏览型号72281L10PFGI8的Datasheet PDF文件第4页浏览型号72281L10PFGI8的Datasheet PDF文件第5页浏览型号72281L10PFGI8的Datasheet PDF文件第6页浏览型号72281L10PFGI8的Datasheet PDF文件第7页 
CMOS SuperSync FIFO™  
65,536 x 9  
IDT72281  
IDT72291  
131,072 x 9  
OBSOLETE PARTS  
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-  
pin Slim Thin Quad Flat Pack (STQFP)  
High-performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
FEATURES:  
Choose among the following memory organizations:  
IDT72281  
IDT72291  
65,536 x 9  
131,072 x 9  
Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable  
settings  
Retransmit operation with fixed, low first word data  
latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag  
can default to one of two preselected offsets  
Program partial flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First  
Word Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance stat
Easily expandable in depth and width  
DESCRIPTION:  
TheIDT72281/72291areexceptionallydeep,highspeed,CMOSFirst-In-  
First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs  
offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe  
following:  
Thelimitationofthefreuencyofoeclockinputwspettotheotherhas  
been removed. The Frequency Select pin (FSeen removed, thus  
it is no longeessary to select which of the two clock inputs, RCLK or  
WCLKis runnng at the higher frequency.  
The perequired by the rit operation is now fixed and short.  
firsworddatalatencyperiomthetimethefirstwordiswrittentoan  
emptyFIFOtothetimecanberead,isnowfixedandshort. (Thevariable  
clock cycle codelay associated with the latency period found on  
previousSuperSeviceshasbeneliminatedonthisSuperSyncfamily.)  
SuperSncFIOsareparticularyappropatefornetwork,video,telecom-  
muications,datacommunicansdotherapplicationsthatneedtobuffer  
largeamountsofdata.  
Independent Read and Write clocks (permit reading and writing  
simultaneously)  
FUNCTIONALBLOCKDIAGRAM  
D0 -D8  
N  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUREGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
65,536 x 9  
131,072 x 9  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
Q0 -Q8  
4675 drw01  
OE  
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MARCH 2013  
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4675/5  

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