Datasheet > 72285L15PFI9

72285L15PFI9

更新时间： 2024-11-07 08:54:55

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
25页	301K
描述
FIFO, 64KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

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72285L15PFI9 数据手册

CMOS SuperSync FIFO™

32,768 x 18

65,536 x 18

IDT72275

IDT72285

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (-40°C to +85°C) is available

FEATURES:

• Choose among the following memory organizations:

IDT72275 — 32,768 x 18

IDT72285 — 65,536 x 18

• Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

DESCRIPTION:

TheIDT72275/72285areexceptionallydeep,highspeed,CMOSFirst-In-

First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs

offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe

following:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is runningatthe higherfrequency.

• The period required by the retransmit operation is now fixed and short.

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clock cycle counting delay associated with the latency period found on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

32,768 x 18

65,536 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

4674 drw 01

Q0 -Q17

IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2003



DSC-4674/4

12 3 4 5 6 7...25

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与72285L15PFI9相关器件

型号	品牌	获取价格	描述	数据表
72285L15TFGI	IDT	获取价格	FIFO, 64KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64
72285L15TFI9	IDT	获取价格	FIFO, 64KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64
72285L20PFGI	IDT	获取价格	FIFO, 64KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72285L20PFI9	IDT	获取价格	FIFO, 64KX18, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
72285L20TFG	IDT	获取价格	FIFO, 64KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64
72285L20TFGI	IDT	获取价格	FIFO, 64KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, STQFP-64
72286	GAMEWELL-FCI	获取价格	Speaker/Strobes
7-2286917-0	TE	获取价格	3 POS. HVP800, 180, 50 SQMM CABLE ASSY
7-2286917-1	TE	获取价格	3 POS. HVP800, 180, 50 SQMM CABLE ASSY
7-2286917-2	TE	获取价格	3 POS. HVP800, 180, 50 SQMM CABLE ASSY

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