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72285L10TFG8 PDF预览

72285L10TFG8

更新时间： 2024-11-09 20:50:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
25页 442K
描述
FIFO, 64KX18, 6.5ns, Synchronous, CMOS, PQFP64

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中文翻译

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72285L10TFG8 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：ObsoleteReach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.55最长访问时间：6.5 ns
最大时钟频率 (fCLK)：100 MHzJESD-30 代码：S-PQFP-G64
JESD-609代码：e3内存密度：1179648 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：3端子数量：64
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX18
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP64,.47SQ,20封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
最大待机电流：0.02 A子类别：FIFOs
最大压摆率：0.09 mA标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
Base Number Matches：1

72285L10TFG8 数据手册

 浏览型号72285L10TFG8的Datasheet PDF文件第2页浏览型号72285L10TFG8的Datasheet PDF文件第3页浏览型号72285L10TFG8的Datasheet PDF文件第4页浏览型号72285L10TFG8的Datasheet PDF文件第5页浏览型号72285L10TFG8的Datasheet PDF文件第6页浏览型号72285L10TFG8的Datasheet PDF文件第7页 
CMOS SuperSync FIFO™  
32,768 x 18  
65,536 x 18  
IDT72275  
IDT72285  
• Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-  
pin Slim Thin Quad Flat Pack (STQFP)  
• High-performance submicron CMOS technology  
• Industrial temperature range (-40°C to +85°C) is available  
FEATURES:  
• Choose among the following memory organizations:  
IDT72275 — 32,768 x 18  
IDT72285 — 65,536 x 18  
• Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs  
• 10ns read/write cycle time (6.5ns access time)  
• Fixed, low first word data latency time  
DESCRIPTION:  
• Auto power down minimizes standby power consumption  
• Master Reset clears entire FIFO  
• Partial Reset clears data, but retains programmable  
settings  
• Retransmit operation with fixed, low first word data  
latency time  
• Empty, Full and Half-Full flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags, each flag  
can default to one of two preselected offsets  
• Program partial flags by either serial or parallel means  
• Select IDT Standard timing (using EF and FF flags) or First  
Word Fall Through timing (using OR and IR flags)  
• Output enable puts data outputs into high impedance state  
• Easily expandable in depth and width  
TheIDT72275/72285areexceptionallydeep,highspeed,CMOSFirst-In-  
First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs  
offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe  
following:  
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas  
been removed. The Frequency Select pin (FS) has been removed, thus  
it is no longer necessary to select which of the two clock inputs, RCLK or  
WCLK, is running at the higher frequency.  
• The period required by the retransmit operation is now fixed and short.  
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan  
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable  
clock cycle counting delay associated with the latency period found on  
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)  
FUNCTIONAL BLOCK DIAGRAM  
D0 -D17  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
32,768 x 18  
65,536 x 18  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
4674 drw 01  
Q0 -Q17  
OE  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2013  
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4674/6  
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