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71V3579YS85BGG8 PDF预览

71V3579YS85BGG8

更新时间: 2024-10-29 10:12:47
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
22页 236K
描述
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119

71V3579YS85BGG8 数据手册

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128K X 36, 256K X 18  
3.3V Synchronous SRAMs  
3.3V I/O, Flow-Through Outputs  
Burst Counter, Single Cycle Deselect  
IDT71V3577YS  
IDT71V3579YS  
IDT71V3577YSA  
IDT71V3579YSA  
Description  
Features  
The IDT71V3577/79 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V3577/79SRAMs containwrite,data,  
address andcontrolregisters.Therearenoregisters inthedataoutput  
path(flow-througharchitecture).InternallogicallowstheSRAMtogen-  
erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe  
endofthe write cycle.  
128K x 36, 256K x 18 memory configurations  
Supports fast access times:  
Commercial:  
– 6.5ns up to 133MHz clock frequency  
– 7.5ns up to 117MHz clock frequency  
CommercialandIndustrial:  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V3577/79canprovidefourcyclesofdata  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBO inputpin.  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array  
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
CS  
0
, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
BWE  
BW , BW  
(1)  
1
2
, BW  
3
, BW  
4
CLK  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
ADV  
ADSC  
ADSP  
LBO  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
NOTE:  
APRIL 2604500tbl 601  
1. BW3 and BW4 are not applicable for the IDT71V3579.  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC-6450/0A  

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