Datasheet > 71V3579YS85BQ

71V3579YS85BQ

更新时间： 2024-10-29 10:37:11

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
22页	629K
描述
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165, FPBGA-165

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71V3579YS85BQ 数据手册

IDT71V3577S

IDT71V3579S

IDT71V3577SA

IDT71V3579SA

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Description

Features

◆

The IDT71V3577/79 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V3577/79SRAMs containwrite,data,

address andcontrolregisters.Therearenoregisters inthedataoutput

path(flow-througharchitecture).InternallogicallowstheSRAMtogen-

erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe

endofthe write cycle.

128K x 36, 256K x 18 memory configurations

◆

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

CommercialandIndustrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V3577/79canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe

arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe

next three rising clock edges. The order of these three addresses are

definedbytheinternalburstcounterandtheLBO inputpin.

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array

PinDescriptionSummary

A0-A17

Address Inputs

Input

Synchronous

Asynchronous

Synchronous

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

BWE

BW , BW

(1)

, BW

CLK

Clock

Input

Output

Input

I/O

N/A

Synchronous

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

NOTE:

FEBRUARY 2⁵0²⁸⁰0^tbl9⁰¹

1. BW3 and BW4 are not applicable for the IDT71V3579.

DSC-5280/08

12 3 4 5 6 7...22

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与71V3579YS85BQ相关器件

型号	品牌	获取价格	描述	数据表
71V3579YS85BQ8	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165
71V3579YS85BQG	IDT	获取价格	Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA165, ROHS COMPLIANT, FBGA-165
71V3579YS85BQG8	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165
71V3579YS85BQGI8	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165
71V3579YS85PFGI	IDT	获取价格	Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
71V3579YS85PFGI8	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PQFP100
71V3579YSA75BGG	IDT	获取价格	Cache SRAM, 256KX18, 7.5ns, CMOS, PBGA119, ROHS COMPLIANT, BGA-119
71V3579YSA75BQG	IDT	获取价格	Cache SRAM, 256KX18, 7.5ns, CMOS, PBGA165, ROHS COMPLIANT, FBGA-165
71V3579YSA80BG8	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119
71V3579YSA80BGI8	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119

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