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71V416L10PH8 PDF预览

71V416L10PH8

更新时间: 2024-10-29 07:37:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 1397K
描述
Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

71V416L10PH8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:0.400 INCH, TSOP2-44
针数:44Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.23最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:18.41 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.18 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

71V416L10PH8 数据手册

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3.3V CMOS Static RAM  
4 Meg (256K x 16-Bit)  
IDT71V416S  
IDT71V416L  
Description  
Features  
TheIDT71V416isa4,194,304-bithigh-speedStaticRAMorganized  
as256Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability  
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-  
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-  
speedmemoryneeds.  
256K x 16 advanced high-speed CMOS Static RAM  
JEDEC Center Power / GND pinout for reduced noise.  
Equal access and cycle times  
– CommercialandIndustrial:10/12/15ns  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
TheIDT71V416has anoutputenablepinwhichoperates as fastas  
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand  
outputsoftheIDT71V416areLVTTL-compatibleandoperationisfroma  
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring  
noclocks orrefreshforoperation.  
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a  
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x  
9mmpackage.  
LVTTL-compatible  
Low power consumption via chip deselect  
Upper and Lower Byte Enable Pins  
Single 3.3V power supply  
Available in 44-pin, 400 mil plastic SOJ package and a 44-  
pin, 400 mil TSOP Type II package and a 48 ball grid array,  
9mm x 9mm package.  
FunctionalBlockDiagram  
Output  
Enable  
Buffer  
OE  
Address  
Buffers  
Row / Column  
Decoders  
A0 - A17  
High  
8
8
8
8
Byte  
I/O 15  
I/O 8  
Output  
Chip  
Select  
Buffer  
Buffer  
CS  
High  
Byte  
Write  
Sense  
Amps  
and  
Write  
Drivers  
4,194,304-bit  
Memory  
Array  
Buffer  
16  
Write  
Enable  
Buffer  
Low  
Byte  
8
8
8
8
WE  
I/O 7  
I/O 0  
Output  
Buffer  
Low  
Byte  
Write  
Buffer  
BHE  
BLE  
Byte  
Enable  
Buffers  
3624 drw 01  
OCTOBER 2008  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-3624/09  

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