Datasheet > 71V35761YSA200BGG

71V35761YSA200BGG

更新时间： 2024-11-06 03:42:15

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
22页	632K
描述
Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, GREEN, BGA-119

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128K x 36, 256K x 18

IDT71V35761S

IDT71V35781S

IDT71V35761SA

IDT71V35781SA

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V35761/781 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1 orderofthesethreeaddressesaredefinedbytheinternalburstcounter

compliant)

andthe LBO inputpin.

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

grid array

100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array.

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

NOTE:

5301 tbl 01

1. BW3 and BW4 are not applicable for the IDT71V35781.

MARCH 2009

DSC-5301/03

12 3 4 5 6 7...22

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与71V35761YSA200BGG相关器件

型号	品牌	获取价格	描述	数据表
71V35761YSA200BQ	IDT	获取价格	Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA165, FBGA-165
71V3576S133BG	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576S133BG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576S133BGG	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, ROHS COMPLIANT, BGA-119
71V3576S133BGG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576S133BGI8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576S133BQG	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA165, ROHS COMPLIANT, FBGA-165
71V3576S133BQI	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA165
71V3576S133BQI8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA165
71V3576S133PF	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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