Datasheet > 71V3576S150BQG

71V3576S150BQG

更新时间： 2024-11-07 07:55:35

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
22页	651K
描述
Cache SRAM, 128KX36, 3.8ns, CMOS, PBGA165, ROHS COMPLIANT, FBGA-165

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中文翻译

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71V3576S150BQG 数据手册

128K x 36, 256K x 18

IDT71V3576S

IDT71V3578S

IDT71V3576SA

IDT71V3578SA

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V3576/78 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V3576/78SRAMs containwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

CommercialandIndustrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

◆

Theburstmodefeatureoffersthehighestlevelofperformancetothe

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.

grid array (fBGA)

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

, BW

, BW ⁽¹⁾

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

5279 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3578.

FEBRUARY 2009

DSC-5279/04

12 3 4 5 6 7...22

中文翻译

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与71V3576S150BQG相关器件

型号	品牌	获取价格	描述	数据表
71V3576S150BQG8	IDT	获取价格	Standard SRAM, 128KX36, 3.8ns, CMOS, PBGA165
71V3576S150BQI	IDT	获取价格	Standard SRAM, 128KX36, 3.8ns, CMOS, PBGA165
71V3576S150BQI8	IDT	获取价格	Standard SRAM, 128KX36, 3.8ns, CMOS, PBGA165
71V3576S150PFG	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
71V3576S150PFG8	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
71V3576S150PFGI	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
71V3576S150PFGI8	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
71V3576SA133BG	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BGG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119

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