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71V3576S150PFGI PDF预览

71V3576S150PFGI

更新时间: 2024-11-07 00:47:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
18页 220K
描述
3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

71V3576S150PFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:QFF, QFP100,.63X.87针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:4.72
最长访问时间:3.8 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):150 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-F100JESD-609代码:e3
长度:20 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFF
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.035 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.26 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:FLAT
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

71V3576S150PFGI 数据手册

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128K x 36, 256K x 18  
IDT71V3576S  
IDT71V3578S  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Description  
Features  
128K x 36, 256K x 18 memory configurations  
The IDT71V3576/78 are high-speed SRAMs organized as  
128Kx36/256Kx18. TheIDT71V3576/78SRAMscontainwrite, data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
Supports high system speed:  
CommercialandIndustrial:  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP)  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata  
forasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
and the LBO input pin.  
The IDT71V3576/78 SRAMs utilize the latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP).  
Pin Description Summary  
A
0
-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW2, BW3, BW4  
(1)  
1
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O  
0-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
N/A  
5279 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V3578.  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
©2015 Integrated Device Technology, Inc.  
DECEMBER 2015  
1
DSC-5279/07  

71V3576S150PFGI 替代型号

型号 品牌 替代类型 描述 数据表
71V3576S150PFGI8 IDT

完全替代

3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V3576S150PFI8 IDT

类似代替

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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