Datasheet > 71V3576S150PFGI8

71V3576S150PFGI8

更新时间： 2024-11-07 00:47:55

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
18页	220K
描述
3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

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71V3576S150PFGI8 数据手册

128K x 36, 256K x 18

IDT71V3576S

IDT71V3578S

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Description

Features

128K x 36, 256K x 18 memory configurations

The IDT71V3576/78 are high-speed SRAMs organized as

128Kx36/256Kx18. TheIDT71V3576/78SRAMscontainwrite, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

CommercialandIndustrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP)

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata

forasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

and the LBO input pin.

◆

The IDT71V3576/78 SRAMs utilize the latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP).

Pin Description Summary

-A17

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

0, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW2, BW3, BW4

(1)

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O

0-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

N/A

5279 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3578.

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

DECEMBER 2015

DSC-5279/07

12 3 4 5 6 7...18

中文翻译

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71V3576S150PFGI8 替代型号

型号	品牌	替代类型	描述	数据表
71V3576S150PFGI	IDT	完全替代	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V3576S150PFI8	IDT	类似代替	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576S150PFI	IDT	类似代替	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin

与71V3576S150PFGI8相关器件

型号	品牌	获取价格	描述	数据表
71V3576SA133BG	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BGG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BGGI8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BGI8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
71V3576SA133BQ	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA165
71V3576SA133BQ8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA165
71V3576SA133BQG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA165
71V3576SA133BQGI	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA165, ROHS COMPLIANT, FBGA-165
71V3576SA133BQGI8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA165

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