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71V3576S150BGG PDF预览

71V3576S150BGG

更新时间: 2024-11-06 14:40:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 651K
描述
Cache SRAM, 128KX36, 3.8ns, CMOS, PBGA119, ROHS COMPLIANT, BGA-119

71V3576S150BGG 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:ROHS COMPLIANT, BGA-119
针数:119Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.75Is Samacsys:N
最长访问时间:3.8 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):150 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e1
长度:22 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:119字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:2.36 mm
最大待机电流:0.03 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.295 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

71V3576S150BGG 数据手册

 浏览型号71V3576S150BGG的Datasheet PDF文件第2页浏览型号71V3576S150BGG的Datasheet PDF文件第3页浏览型号71V3576S150BGG的Datasheet PDF文件第4页浏览型号71V3576S150BGG的Datasheet PDF文件第5页浏览型号71V3576S150BGG的Datasheet PDF文件第6页浏览型号71V3576S150BGG的Datasheet PDF文件第7页 
128K x 36, 256K x 18  
IDT71V3576S  
IDT71V3578S  
IDT71V3576SA  
IDT71V3578SA  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
The IDT71V3576/78 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V3576/78SRAMs containwrite,data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
Supports high system speed:  
CommercialandIndustrial:  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.  
grid array (fBGA)  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0
, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
1
2
, BW  
3
, BW (1)  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
5279 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V3578.  
FEBRUARY 2009  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5279/04  

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