128K X 36
IDT71V25761YS/S
3.3VSynchronousSRAMs
2.5V I/O, Pipelined Outputs,
Burst Counter, Single Cycle Deselect
Features
Description
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128K x 36 memory configuration
TheIDT71V25761arehigh-speedSRAMsorganizedas128Kx36.
The IDT71V25761 SRAMs contain write, data, address and control
registers. InternallogicallowstheSRAMtogenerateaself-timedwrite
basedupona decisionwhichcanbe leftuntilthe endofthe write cycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V25761canprovidefourcyclesofdatafor
a single address presented to the SRAM. An internal burst address
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
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Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
CommercialandIndustrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
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Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
Compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball 100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
orderofthesethreeaddressesaredefinedbytheinternalburstcounter
andthe LBO inputpin.
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The IDT71V25761 SRAMs utilize IDT’s latest high-performance
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grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0
, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW , BW
(1)
1
2
, BW
3
, BW
4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
TRST
ZZ
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
5297 tbl 01
MAY 2010
1
©2010IntegratedDeviceTechnology,Inc.
DSC-5297/05