Datasheet > 71V257780BG

71V257780BG

更新时间： 2024-09-29 04:56:39

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	520K
描述
Standard SRAM, 128KX36, 8ns, CMOS, PBGA119

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71V257780BG 数据手册

128K x 36, 256K x 18

IDT71V2577

IDT71V2579

3.3V Synchronous SRAMs

2.5V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Description

Features

◆

The IDT71V2577/79 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,

address andcontrolregisters.Therearenoregisters inthedataoutput

path (flow-through architecture). Internal logic allows the SRAM to

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

128K x 36, 256K x 18 memory configurations

◆

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

CommercialandIndustrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

theendofthewritecycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata

fora single address presentedtothe SRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe

arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe

next three rising clock edges. The order of these three addresses are

definedbytheinternalburstcounterandtheLBOinputpin.

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array (fBGA)

The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A -A

Address Inputs

Input

Synchronous

Asynchronous

Synchronous

Chip Enable

CS , CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

BWE

(1)

BW , BW , BW , BW

CLK

ADV

ADSC

ADSP

LBO

Clock

Input

I/O

N/A

Synchronous

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Asynchronous

Synchronous

N/A

I/O -I/O , I/O -I/O

Data Input / Output

DD DDQ

V , V

Core Power, I/O Power

Ground

Supply

N/A

4877 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V2579.

OCTOBER 2000

DSC-4877/06

12 3 4 5 6 7...23

中文翻译

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与71V257780BG相关器件

型号	品牌	获取价格	描述	数据表
71V257780BQI	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PBGA165
71V257780PF	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PQFP100
71V257780PFI	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PQFP100
71V25781S166BG8	IDT	获取价格	PBGA-119, Reel
71V25781S166BGI	IDT	获取价格	PBGA-119, Tray
71V25781S166BQI	IDT	获取价格	Cache SRAM, 256KX18, 3.5ns, CMOS, PBGA165, FBGA-165
71V25781S166PF	IDT	获取价格	TQFP-100, Tray
71V25781S166PF9	IDT	获取价格	TQFP-100, Tray
71V25781S166PFI8	IDT	获取价格	TQFP-100, Reel
71V25781S183BG	IDT	获取价格	PBGA-119, Tray

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