Datasheet > 71V2576S150PFI8

71V2576S150PFI8

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	627K
描述
TQFP-100, Reel

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中文翻译

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数据手册

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71V2576S150PFI8 数据手册

128K X 36, 256K X 18

IDT71V25761S

IDT71V25781S

IDT71V25761SA

IDT71V25781SA

3.3VSynchronousSRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

TheIDT71V25761/781arehigh-speedSRAMs organizedas 128K

x 36/256K x 18. The IDT71V25761/781 SRAMs contain write, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V25761/718canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

Compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

TheIDT71V25761/781SRAMsutilizeIDT’slatesthigh-performance

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

grid array

100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

5297 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V25781.

MARCH 2009

DSC-5297/03

12 3 4 5 6 7...22

中文翻译

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与71V2576S150PFI8相关器件

型号	品牌	获取价格	描述	数据表
71V2576S150PFI9	IDT	获取价格	TQFP-100, Tray
71V2576YS150PFG8	IDT	获取价格	TQFP-100, Reel
71V2576YS150PFI	IDT	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
71V257780BG	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PBGA119
71V257780BQI	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PBGA165
71V257780PF	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PQFP100
71V257780PFI	IDT	获取价格	Standard SRAM, 128KX36, 8ns, CMOS, PQFP100
71V25781S166BG8	IDT	获取价格	PBGA-119, Reel
71V25781S166BGI	IDT	获取价格	PBGA-119, Tray
71V25781S166BQI	IDT	获取价格	Cache SRAM, 256KX18, 3.5ns, CMOS, PBGA165, FBGA-165

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