Datasheet > 71P74804S333BQ

71P74804S333BQ

更新时间： 2024-09-16 19:24:23

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
22页	303K
描述
CABGA-165, Tray

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技术参数
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71P74804S333BQ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	CABGA
包装说明：	TBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.88
最长访问时间：	0.45 ns	最大时钟频率 (fCLK)：	333 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	QDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最小待机电流：	1.7 V
子类别：	SRAMs	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	13 mm	Base Number Matches：	1

71P74804S333BQ 数据手册

Advance

Information

IDT71P74204

IDT71P74104

IDT71P74804

IDT71P74604

18Mb Pipelined

QDR™II SRAM

Burst of 4

Description

Features

The IDT QDRII Burst of four SRAMs are high-speed synchronous

memories with independent, double-data-rate (DDR), read and write

data ports. This scheme allows simultaneous read and write access for

the maximum device throughput, with four data items passed with each

read or write. Four data word transfers occur per clock cycle, providing

quad-data-rate(QDR)performance. ComparingthiswithstandardSRAM

common I/O (CIO), single data rate (SDR) devices, a four to one in-

crease in data access is achieved at equivalent clock speeds. Consider-

ing that QDRII allows clock speeds in excess of standard SRAM de-

vices, the throughput can be increased well beyond four to one in most

applications.

◆

18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)

Separate, Independent Read and Write Data Ports

Supports concurrent transactions

◆

Dual Echo Clock Output

4-Word Burst on all SRAM accesses

Multiplexed Address Bus One Read or One Write request

per clock cycle

◆

DDR (Double Data Rate) Data Bus

Four word burst data per two clock cycles on

each port

Four word transfers per clock cycle

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

◆

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

◆

Scalable output drivers

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

The QDRII has a single SDR address bus with read addresses and

write addresses multiplexed. The read and write addresses interleave

with each occurring a maximum of every other cycle. In the event that no

operation takes place on a cycle, the subsequest cycle may begin with

either a read or write. During write operations, the writing of individual

bytes may be blocked through the use of byte or nibble write control

signals.

Output Impedance adjustable from 35 ohms to 70

ohms

◆

1.8V Core Voltage (VDD)

165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package

JTAG Interface

The QDRII has echo clocks, which provide the user with a clock

Functional Block Diagram

(Note1)

DATA

REG

WRITE DRIVER

(Note2)

ADD

REG

(Note1)

18M

MEMORY

ARRAY

CTRL

LOGIC

(Note3)

BWx

CLK

GEN

SELECT OUTPUT CONTROL

6111 drw16

Notes

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the

and there are 2 signal lines.

is a “nibble write”

MARCH 2004

DSC-6111/00

12 3 4 5 6 7...22

中文翻译

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与71P74804S333BQ相关器件

型号	品牌	获取价格	描述	数据表
71P79104S167BQ	IDT	获取价格	Standard SRAM, 2MX9, 0.5ns, CMOS, PBGA165
71P79104S167BQI	IDT	获取价格	Standard SRAM, 2MX9, 0.5ns, CMOS, PBGA165
71P79104S200BQ	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79104S200BQI	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79104S250BQ	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79104S250BQI	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79604S167BQI8	IDT	获取价格	CABGA-165, Reel
71P79604S200BQ	IDT	获取价格	CABGA-165, Tray
71P79604S200BQ8	IDT	获取价格	CABGA-165, Reel
71P79604S200BQI	IDT	获取价格	CABGA-165, Tray

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