Datasheet > 71P79604S333BQI8

71P79604S333BQI8

更新时间： 2024-11-07 06:28:03

品牌	Logo	应用领域
艾迪悌 - IDT		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
23页	630K
描述
CABGA-165, Reel

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技术参数
数据手册

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71P79604S333BQI8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	CABGA
包装说明：	,	针数：	165
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-609代码：	e0	内存集成电路类型：	DDR SRAM
湿度敏感等级：	3	峰值回流温度（摄氏度）：	225
端子面层：	Tin/Lead (Sn/Pb)	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

71P79604S333BQI8 数据手册

IDT71P79204

IDT71P79104

IDT71P79804

IDT71P79604

18Mb Pipelined

DDR™II SIO SRAM

Burst of 2

Description

Features

◆ 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)

◆ Separate, Independent Read and Write Data Ports

- Supports concurrent transactions

The IDT DDRII^TMBurst of two SIO SRAMs are high-speed syn-

chronous memories with independent, double-data-rate (DDR), read

and write data ports with two data items passed with each read or write.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the DDRII SIO are unidirectional and can be optimized

for signal integrity at very high bus speeds. Memory bandwidth is higher

than DDR SRAM with bi-directional data buses as separate read and

write ports eliminate bus turn around cycle. Separate read and write

ports also enable easy depth expansion. Each port can be selected

independantly with a R/W input shared among all SRAMs and provide

a new LD load control signal for each bank. The DDRII SIO has scal-

able output impedance on its data output bus and echo clocks, allowing

the user to tune the bus for low noise and high performance.

◆ Dual Echo Clock Output

◆ 2-Word Burst on all SRAM accesses

◆ MultiplexedAddress Bus

- One Read or one Write request per clock cycle

◆ DDR (Double Data Rate) Data Bus

- Two word burst data per clock

◆ Depth expansion through Control Logic

◆ HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V

to 1.9V.

◆ Scalable output drivers

- Can drive HSTL, 1.8V TTLor any voltage level from 1.4V to 1.9V.

- Output Impedance adjustable from 35 ohms to 70 ohms

◆ 1.8V Core Voltage (VDD)

◆ 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package

◆ JTAG Interface

The DDRII SIO has a single SDR address bus with multiplexed

read and write addresses. The read/write and load control inputs are

received on the first half of the clock cycle. The byte and nibble write

signals are received on both halves of the clock cycle simultaneously

with the data they are controlling on the data input bus.

The DDRII SIO has echo clocks, which provide the user with a

clock that is precisely timed to the data output, and tuned with matching

impedance and signal quality. The user can use the echo clock for

downstream clocking of the data. Echo clocks eliminate the need for the

user to produce alternate clocks with precise timing, positioning, and

signal qualities to guarantee data capture. Since the echo clocks are

Functional Block Diagram

(Note1)

DATA

REG

DATA

REG

(Note1)

WRITE DRIVER

(Note2)

(Note3)

ADD

REG

(Note2)

(Note4)

(Note1)

18M

MEMORY

ARRAY

R/W

BWx

CTRL

LOGIC

CLK

GEN

SELECT OUTPUT CONTROL

6432 drw 16

Notes:

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2

signal lines.

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

NOVEMBER 2005

DSC-6432/01

12 3 4 5 6 7...23

中文翻译

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与71P79604S333BQI8相关器件

型号	品牌	获取价格	描述	数据表
71P79804167BQ	IDT	获取价格	Standard SRAM, 1MX18, 0.5ns, CMOS, PBGA165
71P79804167BQG	IDT	获取价格	Standard SRAM, 1MX18, 0.5ns, CMOS, PBGA165
71P79804167BQGI	IDT	获取价格	Standard SRAM, 1MX18, 0.5ns, CMOS, PBGA165
71P79804167BQI8	IDT	获取价格	Standard SRAM, 1MX18, 0.5ns, CMOS, PBGA165
71P79804200BQ	IDT	获取价格	Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165
71P79804200BQI	IDT	获取价格	Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165
71P79804250BQ	IDT	获取价格	Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165
71P79804250BQG	IDT	获取价格	Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165
71P79804250BQGI	IDT	获取价格	Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165
71P79804250BQGI8	IDT	获取价格	Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165

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