Datasheet > 71P79104S167BQI

71P79104S167BQI

更新时间： 2024-11-06 19:42:23

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
23页	629K
描述
Standard SRAM, 2MX9, 0.5ns, CMOS, PBGA165

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71P79104S167BQI 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	not_compliant	风险等级：	5.88
最长访问时间：	0.5 ns	最大时钟频率 (fCLK)：	167 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	内存密度：	18874368 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	9
湿度敏感等级：	3	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2MX9
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	最大待机电流：	0.335 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.65 mA	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
Base Number Matches：	1

71P79104S167BQI 数据手册

IDT71P79204

IDT71P79104

IDT71P79804

IDT71P79604

18Mb Pipelined

DDR™II SIO SRAM

Burst of 2

Description

Features

◆ 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)

◆ Separate, Independent Read and Write Data Ports

- Supports concurrent transactions

The IDT DDRII^TMBurst of two SIO SRAMs are high-speed syn-

chronous memories with independent, double-data-rate (DDR), read

and write data ports with two data items passed with each read or write.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the DDRII SIO are unidirectional and can be optimized

for signal integrity at very high bus speeds. Memory bandwidth is higher

than DDR SRAM with bi-directional data buses as separate read and

write ports eliminate bus turn around cycle. Separate read and write

ports also enable easy depth expansion. Each port can be selected

independantly with a R/W input shared among all SRAMs and provide

a new LD load control signal for each bank. The DDRII SIO has scal-

able output impedance on its data output bus and echo clocks, allowing

the user to tune the bus for low noise and high performance.

◆ Dual Echo Clock Output

◆ 2-Word Burst on all SRAM accesses

◆ MultiplexedAddress Bus

- One Read or one Write request per clock cycle

◆ DDR (Double Data Rate) Data Bus

- Two word burst data per clock

◆ Depth expansion through Control Logic

◆ HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V

to 1.9V.

◆ Scalable output drivers

- Can drive HSTL, 1.8V TTLor any voltage level from 1.4V to 1.9V.

- Output Impedance adjustable from 35 ohms to 70 ohms

◆ 1.8V Core Voltage (VDD)

◆ 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package

◆ JTAG Interface

The DDRII SIO has a single SDR address bus with multiplexed

read and write addresses. The read/write and load control inputs are

received on the first half of the clock cycle. The byte and nibble write

signals are received on both halves of the clock cycle simultaneously

with the data they are controlling on the data input bus.

The DDRII SIO has echo clocks, which provide the user with a

clock that is precisely timed to the data output, and tuned with matching

impedance and signal quality. The user can use the echo clock for

downstream clocking of the data. Echo clocks eliminate the need for the

user to produce alternate clocks with precise timing, positioning, and

signal qualities to guarantee data capture. Since the echo clocks are

Functional Block Diagram

(Note1)

DATA

REG

DATA

REG

(Note1)

WRITE DRIVER

(Note2)

(Note3)

ADD

REG

(Note2)

(Note4)

(Note1)

18M

MEMORY

ARRAY

R/W

BWx

CTRL

LOGIC

CLK

GEN

SELECT OUTPUT CONTROL

6432 drw 16

Notes:

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2

signal lines.

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

NOVEMBER 2005

DSC-6432/01

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与71P79104S167BQI相关器件

型号	品牌	获取价格	描述	数据表
71P79104S200BQ	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79104S200BQI	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79104S250BQ	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79104S250BQI	IDT	获取价格	Standard SRAM, 2MX9, 0.45ns, CMOS, PBGA165
71P79604S167BQI8	IDT	获取价格	CABGA-165, Reel
71P79604S200BQ	IDT	获取价格	CABGA-165, Tray
71P79604S200BQ8	IDT	获取价格	CABGA-165, Reel
71P79604S200BQI	IDT	获取价格	CABGA-165, Tray
71P79604S200BQI8	IDT	获取价格	CABGA-165, Reel
71P79604S250BQ8	IDT	获取价格	CABGA-165, Reel

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