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70V26S55GG8 PDF预览

70V26S55GG8

更新时间: 2024-11-08 19:47:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
19页 499K
描述
SRAM

70V26S55GG8 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.67Base Number Matches:1

70V26S55GG8 数据手册

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70V26S/L  
HIGH-SPEED 3.3V  
16K x 16 DUAL-PORT  
STATIC RAM  
Features  
IDT70V26 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:25/35/55ns(max.)  
Low-power operation  
– IDT70V26S  
Active: 300mW (typ.)  
Standby: 3.3mW (typ.)  
– IDT70V26L  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 84-pin PGA and PLCC  
Active: 300mW (typ.)  
Standby: 660μW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
Green parts available, see ordering information  
bus compatibility  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UB  
UBL  
LBL  
LBR  
CE  
OE  
L
L
CE  
R
OER  
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
(1,2)  
(1,2)  
L
BUSY  
BUSY  
R
A
13L  
A
13R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
0R  
14  
14  
ARBITRATION  
SEMAPHORE  
LOGIC  
CEL  
CER  
SEMR  
SEM  
L
M/S  
2945 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs are non-tri-stated push-pull.  
JULY 2019  
1
DSC 2945/19  

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