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70V25S35JGI PDF预览

70V25S35JGI

更新时间: 2024-11-30 21:08:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 177K
描述
Dual-Port SRAM, 8KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84

70V25S35JGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ,针数:84
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.13
最长访问时间:35 nsJESD-30 代码:S-PQCC-J84
JESD-609代码:e3长度:29.3116 mm
内存密度:131072 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端子数量:84字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX16封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:29.3116 mmBase Number Matches:1

70V25S35JGI 数据手册

 浏览型号70V25S35JGI的Datasheet PDF文件第2页浏览型号70V25S35JGI的Datasheet PDF文件第3页浏览型号70V25S35JGI的Datasheet PDF文件第4页浏览型号70V25S35JGI的Datasheet PDF文件第5页浏览型号70V25S35JGI的Datasheet PDF文件第6页浏览型号70V25S35JGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
8K x 16 DUAL-PORT  
STATIC RAM  
IDT70V25S/L  
Features  
True Dual-Ported memory cells which allow simultaneous  
IDT70V25 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
reads of the same memory location  
High-speed access  
– Commercial:15/20/25/35/55ns(max.)  
Industrial:20/25/35/55ns(max.)  
Low-power operation  
IDT70V25S  
Active:400mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V25L  
Active:380mW(typ.)  
Standby: 660µW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
Functional Block Diagram  
WL  
R/  
R/WR  
UBR  
UBL  
LBR  
CER  
OER  
LBL  
CEL  
OEL  
,
I/O8L-I/O15L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
I/O0L-I/O7L  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
A12R  
A12L  
A0L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CER  
OER  
R/WR  
CEL  
OEL  
R/WL  
SEMR  
INTR  
SEML  
INTL  
(2)  
(2)  
M/S  
2944 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
MAY 2000  
1
DSC-2944/8  
©2000IntegratedDeviceTechnology,Inc.  

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