Datasheet > 70V26

70V26

更新时间： 2024-12-02 14:57:43

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
19页	529K
描述
16K x 16 3.3V Dual-Port RAM

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中文翻译

获取价格

数据手册

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70V26 数据手册

70V26S/L

HIGH-SPEED 3.3V

16K x 16 DUAL-PORT

STATIC RAM

◆

Features

IDT70V26 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Commercial:25/35/55ns(max.)

Low-power operation

◆

– IDT70V26S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V26L

◆

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 84-pin PGA and PLCC

Active: 300mW (typ.)

Standby: 660μW (typ.)

Separate upper-byte and lower-byte control for multiplexed

Green parts available, see ordering information

◆

bus compatibility

Functional Block Diagram

R/W

UBL

LBL

LBR

OER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSY

13L

13R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

SEMAPHORE

LOGIC

CEL

CER

SEMR

SEM

M/S

2945 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

JULY 2019

DSC 2945/19

12 3 4 5 6 7...19

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