Datasheet > 70V261

70V261

更新时间： 2023-12-20 18:44:53

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
19页	258K
描述
16K x 16 3.3V Dual-Port RAM w/Int

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数据手册

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70V261 数据手册

HIGH-SPEED 3.3V

16K x 16 DUAL-PORT

STATIC RAM

70V261S/L

◆

Features

IDT70V261 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP, Thin Quad Plastic Flatpack

Industrial temperature range (-40°C to +85°C) is available

for selected speed

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial: 25/35ns (max.)

– Industrial: 25ns (max.)

Low-power operation

◆

– IDT70V261S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V261L

◆

Active: 300mW (typ.)

Standby: 660μW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

bus compatibility

Functional Block Diagram

R/W

UBL

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSY

13R

13L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INT

(2)

INTR

M/S

3040 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

Jun.04.21

12 3 4 5 6 7...19

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