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70V16L20JI8 PDF预览

70V16L20JI8

更新时间: 2024-11-09 15:26:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
18页 163K
描述
Dual-Port SRAM, 16KX9, 20ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

70V16L20JI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
Reach Compliance Code:not_compliant风险等级:5.92
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e0
内存密度:147456 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9湿度敏感等级:1
功能数量:1端口数量:2
端子数量:68字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX9输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.195 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

70V16L20JI8 数据手册

 浏览型号70V16L20JI8的Datasheet PDF文件第2页浏览型号70V16L20JI8的Datasheet PDF文件第3页浏览型号70V16L20JI8的Datasheet PDF文件第4页浏览型号70V16L20JI8的Datasheet PDF文件第5页浏览型号70V16L20JI8的Datasheet PDF文件第6页浏览型号70V16L20JI8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
16/8K X 9 DUAL-PORT  
STATIC RAM  
IDT70V16/5S/L  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flag  
On-chip port arbitration logic  
– Commercial:15/20/25ns(max.)  
– Industrial: 20ns (max.)  
Low-power operation  
– IDT70V16/5S  
Full on-chip hardware support of semaphore signaling  
between ports  
Active:430mW(typ.)  
Standby: 3.3mW (typ.)  
– IDT70V16/5L  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (+0.3V) power supply  
Available in 68-pin PLCC and an 80-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:415mW(typ.)  
Standby:660µW(typ.)  
IDT70V16/5 easily expands data bus width to 18 bits or  
FunctionalBlockDiagram  
OEL  
OER  
CER  
CEL  
R/WR  
R/W  
L
I/O0L- I/O8L  
I/O0R-I/O8R  
I/O  
I/O  
Control  
Control  
BUSY (2,3)  
L
(2,3)  
BUSY  
R
(1)  
13L  
(1)  
A
A
13R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0R  
A0L  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
SEM  
L
SEM  
R
M/S  
(3)  
(3)  
INTL  
INT  
R
5669 drw 01  
NOTES:  
1. A13 is a NC for IDT70V15.  
2. In MASTER mode: BUSY is an output and is a push-pull driver  
In SLAVE mode: BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.  
OCTOBER 2004  
1
DSC 5669/2  
©2004 IntegratedDeviceTechnology,Inc.  

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