Datasheet > 70V17L15PFI8

70V17L15PFI8

更新时间： 2024-11-25 06:19:47

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	158K
描述
TQFP-100, Reel

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中文翻译

获取价格

数据手册

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70V17L15PFI8 数据手册

PRELIMINARY

IDT70V17L

HIGH-SPEED 3.3V

32K x 9 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

– Commercial:15/20ns (max.)

– Industrial:20ns (max.)

Low-power operation

◆

– IDT70V17L

Active: 440mW (typ.)

Standby: 660µW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT70V17 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

than one device

◆

Functional Block Diagram

R/W_L

CE0L

CE1L

R/W_R

OE_L

OE_R

I/O

Control

I/O

Control

0-8L

I/O

0-8R

I/O

(1,2)

BUSY

32Kx9

14L

14R

MEMORY

ARRAY

70V17

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE _0L

CE_1L

CE_0R

CE_1R

OE_R

R/W_L

R/WR

SEM

INT

SEM

(2)

INT

M/S⁽¹⁾

NOTES:

5643 drw 01

1. BUSY is an input as a Slave (M/S=V^IL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JUNE 2003

DSC-5643/1

12 3 4 5 6 7...17

中文翻译

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