Datasheet > 70V18L15PFGI8

70V18L15PFGI8

更新时间： 2024-11-09 19:52:27

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
18页	164K
描述
Dual-Port SRAM

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中文翻译

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技术参数
数据手册

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70V18L15PFGI8 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82
内存集成电路类型：	DUAL-PORT SRAM	Base Number Matches：	1

70V18L15PFGI8 数据手册

HIGH-SPEED 3.3V

64K x 9 DUAL-PORT

STATIC RAM

70V18L

OBSOLETEPART

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

IDT70V18 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

◆

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

Low-power operation

◆

– IDT70V18L

◆

Active: 440mW (typ.)

Standby: 660µW (typ.)

Dual chip enables allow for depth expansion without

external logic

Busy and Interrupt Flags

On-chip port arbitration logic

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

◆

Functional Block Diagram

R/W_L

CE0L

CE1L

R/W_R

CE0

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

0-8L

I/O

0-8R

I/O

(1,2)

BUSY

64Kx9

MEMORY

ARRAY

70V18

15L

15R

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE _0L

CE_1L

CE_0R

CE_1R

OE_R

R/W_L

R/W

SEM

INT

SEM

(2)

INT

M/S⁽¹⁾

4854 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

DECEMBER 2017

DSC-4854/7

12 3 4 5 6 7...18

中文翻译

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